A conventional voltage-controlled oscillator (VCO) is shown in FIG. 1. Such a VCO is used in a phase lock loop (PLL). The power supply rejection ratio (PSRR) feature of the VCO is decisive of its jitter. As shown in FIG. 1, a VCO circuit comprises a charge pump circuit 10 and a ring oscillator 20. The charge pump circuit 10 comprises two charge pumps, PUMP-up and PUMP-down. With the ON and OFF operations of two switches UP and DOWN in sequence, the voltage at PUMP may be controlled. VDD is power supplied to the circuit. In such a circuit, the voltage at PUMP changes along with the change of the voltage of VDD. The voltage of VDD-PUMT is transformed into current by transistor 11 and into a bias by transistor 12. The bias is supplied to the ring oscillator 20.
The ring oscillator 20 comprises several oscillator circuits 21, 22 and 23 which are connected as a ring. Bias supplied by transistor 12 drives the ring oscillator 20 to generate oscillation. With this circuit, oscillation at a pre-determined frequency may be generated by the ring oscillator 20 according to the difference of the voltage at PUMP and the VDD voltage.
The above-mentioned conventional voltage-controlled oscillator is capable of generating oscillations under a pre-determined frequency according to the voltage of the input voltage. However, when the voltage of VDD has a sudden change, the oscillation frequency of the oscillator will raise in response to the raise of the VDD voltage. As a result, an undesired change will be caused to the oscillation frequency of the ring oscillator.
It is thus a need in the industry to provide an improved voltage-controlled oscillator in which the influence of the voltage of the power supply to the oscillator frequency of the oscillator may be moderated.